st,stm32wl-rcc

Vendor: STMicroelectronics

Description

STM32WL Reset and Clock controller node.
For more description confere st,stm32-rcc.yaml

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

Constant value: 2

clock-frequency

int

default frequency in Hz for clock output

This property is required.

apb1-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

apb2-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

undershoot-prevention

boolean

On some parts, it could be required to set up highest core frequencies
(>80MHz) in two steps in order to prevent undershoot.
This is done by applying an intermediate AHB prescaler before switching
System Clock source to PLL. Once done, prescaler is set back to expected
value.

cpu1-prescaler

int

CPU1 prescaler. Sets a HCLK1 frequency (Core frequency)
lower than SYSCLK frequency.
The HCLK1 clocks CPU1, AHB1, AHB2, AHB3 and SRAM1.

This property is required.

Legal values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32, 64, 128, 256, 512

cpu2-prescaler

int

CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
(A.K.A C2HPRE)

Legal values: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512

ahb3-prescaler

int

HCLK3 shared prescaler (AHB3, Flash memory, SRAM1 and SRAM2).
(A.K.A SHDHPRE)

This property is required.

Legal values: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512

Specifier cell names

  • clock cells: bus, bits