|
Zephyr API 3.6.99
|
Loading...
Searching...
No Matches
Go to the documentation of this file.
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
10#define WIFI_MAC_INTR_SOURCE 0
11#define WIFI_MAC_NMI_SOURCE 1
12#define WIFI_BB_INTR_SOURCE 2
13#define BT_MAC_INTR_SOURCE 3
14#define BT_BB_INTR_SOURCE 4
15#define BT_BB_NMI_SOURCE 5
16#define RWBT_INTR_SOURCE 6
17#define RWBLE_INTR_SOURCE 7
18#define RWBT_NMI_SOURCE 8
19#define RWBLE_NMI_SOURCE 9
20#define SLC0_INTR_SOURCE 10
21#define SLC1_INTR_SOURCE 11
22#define UHCI0_INTR_SOURCE 12
23#define UHCI1_INTR_SOURCE 13
24#define TG0_T0_LEVEL_INTR_SOURCE 14
25#define TG0_T1_LEVEL_INTR_SOURCE 15
26#define TG0_WDT_LEVEL_INTR_SOURCE 16
27#define TG0_LACT_LEVEL_INTR_SOURCE 17
28#define TG1_T0_LEVEL_INTR_SOURCE 18
29#define TG1_T1_LEVEL_INTR_SOURCE 19
30#define TG1_WDT_LEVEL_INTR_SOURCE 20
31#define TG1_LACT_LEVEL_INTR_SOURCE 21
32#define GPIO_INTR_SOURCE 22
33#define GPIO_NMI_SOURCE 23
34#define FROM_CPU_INTR0_SOURCE 24
35#define FROM_CPU_INTR1_SOURCE 25
36#define FROM_CPU_INTR2_SOURCE 26
37#define FROM_CPU_INTR3_SOURCE 27
38#define SPI0_INTR_SOURCE 28
39#define SPI1_INTR_SOURCE 29
40#define SPI2_INTR_SOURCE 30
41#define SPI3_INTR_SOURCE 31
42#define I2S0_INTR_SOURCE 32
43#define I2S1_INTR_SOURCE 33
44#define UART0_INTR_SOURCE 34
45#define UART1_INTR_SOURCE 35
46#define UART2_INTR_SOURCE 36
47#define SDIO_HOST_INTR_SOURCE 37
48#define ETH_MAC_INTR_SOURCE 38
49#define PWM0_INTR_SOURCE 39
50#define PWM1_INTR_SOURCE 40
51#define PWM2_INTR_SOURCE 41
52#define PWM3_INTR_SOURCE 42
53#define LEDC_INTR_SOURCE 43
54#define EFUSE_INTR_SOURCE 44
55#define TWAI_INTR_SOURCE 45
56#define CAN_INTR_SOURCE TWAI_INTR_SOURCE
57#define RTC_CORE_INTR_SOURCE 46
58#define RMT_INTR_SOURCE 47
59#define PCNT_INTR_SOURCE 48
60#define I2C_EXT0_INTR_SOURCE 49
61#define I2C_EXT1_INTR_SOURCE 50
62#define RSA_INTR_SOURCE 51
63#define SPI1_DMA_INTR_SOURCE 52
64#define SPI2_DMA_INTR_SOURCE 53
65#define SPI3_DMA_INTR_SOURCE 54
66#define WDT_INTR_SOURCE 55
67#define TIMER1_INTR_SOURCE 56
68#define TIMER2_INTR_SOURCE 57
69#define TG0_T0_EDGE_INTR_SOURCE 58
70#define TG0_T1_EDGE_INTR_SOURCE 59
71#define TG0_WDT_EDGE_INTR_SOURCE 60
72#define TG0_LACT_EDGE_INTR_SOURCE 61
73#define TG1_T0_EDGE_INTR_SOURCE 62
74#define TG1_T1_EDGE_INTR_SOURCE 63
75#define TG1_WDT_EDGE_INTR_SOURCE 64
76#define TG1_LACT_EDGE_INTR_SOURCE 65
77#define MMU_IA_INTR_SOURCE 66
78#define MPU_IA_INTR_SOURCE 67
79#define CACHE_IA_INTR_SOURCE 68
80#define MAX_INTR_SOURCE 69
85#define IRQ_DEFAULT_PRIORITY 0
87#define ESP_INTR_FLAG_SHARED (1<<8)