Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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eth_nxp_enet_qos.h
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1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_QOS_H__
8#define ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_QOS_H__
9
10#include <fsl_device_registers.h>
12
13/* Different platforms named the peripheral different in the register definitions */
14#ifdef CONFIG_SOC_FAMILY_NXP_MCX
15#undef ENET
16#define ENET_QOS_NAME ENET
17#define ENET_QOS_ALIGNMENT 4
18typedef ENET_Type enet_qos_t;
19#else
20#error "ENET_QOS not enabled on this SOC series"
21#endif
22
23#define _PREFIX_UNDERLINE(x) _##x
24#define _ENET_QOS_REG_FIELD(reg, field) MACRO_MAP_CAT(_PREFIX_UNDERLINE, reg, field, MASK)
25#define _ENET_QOS_REG_MASK(reg, field) CONCAT(ENET_QOS_NAME, _ENET_QOS_REG_FIELD(reg, field))
26
27/* Deciphers value of a field from a read value of an enet qos register
28 *
29 * reg: name of the register
30 * field: name of the bit field within the register
31 * val: value that had been read from the register
32 */
33#define ENET_QOS_REG_GET(reg, field, val) FIELD_GET(_ENET_QOS_REG_MASK(reg, field), val)
34
35/* Prepares value of a field for a write to an enet qos register
36 *
37 * reg: name of the register
38 * field: name of the bit field within the register
39 * val: value to put into the field
40 */
41#define ENET_QOS_REG_PREP(reg, field, val) FIELD_PREP(_ENET_QOS_REG_MASK(reg, field), val)
42
43
44#define ENET_QOS_ALIGN_ADDR_SHIFT(x) (x >> (ENET_QOS_ALIGNMENT >> 1))
45
48 const struct device *clock_dev;
50 enet_qos_t *base;
51};
52#define ENET_QOS_MODULE_CFG(module_dev) ((struct nxp_enet_qos_config *) module_dev->config)
53
54#endif /* ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_H__ */
Public Clock Control APIs.
void * clock_control_subsys_t
clock_control_subsys_t is a type to identify a clock controller sub-system.
Definition: clock_control.h:58
Runtime device structure (in ROM) per driver instance.
Definition: device.h:399
Definition: eth_nxp_enet_qos.h:46
enet_qos_t * base
Definition: eth_nxp_enet_qos.h:50
clock_control_subsys_t clock_subsys
Definition: eth_nxp_enet_qos.h:49
const struct device * clock_dev
Definition: eth_nxp_enet_qos.h:48
const struct pinctrl_dev_config * pincfg
Definition: eth_nxp_enet_qos.h:47
Pin controller configuration for a given device.
Definition: pinctrl.h:62