mii.h

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/*
 * Copyright (c) 2016 Piotr Mienkowski
 * Copyright 2022 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_NET_MII_H_
#define ZEPHYR_INCLUDE_NET_MII_H_
 
/* MII management registers */
#define MII_BMCR       0x0
#define MII_BMSR       0x1
#define MII_PHYID1R    0x2
#define MII_PHYID2R    0x3
#define MII_ANAR       0x4
#define MII_ANLPAR     0x5
#define MII_ANER       0x6
#define MII_ANNPTR     0x7
#define MII_ANLPRNPR   0x8
#define MII_1KTCR 0x9
#define MII_1KSTSR 0xa
#define MII_MMD_ACR    0xd
#define MII_MMD_AADR   0xe
#define MII_ESTAT      0xf
 
/* Basic Mode Control Register (BMCR) bit definitions */
#define MII_BMCR_RESET             (1 << 15)
#define MII_BMCR_LOOPBACK          (1 << 14)
#define MII_BMCR_SPEED_LSB         (1 << 13)
#define MII_BMCR_AUTONEG_ENABLE    (1 << 12)
#define MII_BMCR_POWER_DOWN        (1 << 11)
#define MII_BMCR_ISOLATE           (1 << 10)
#define MII_BMCR_AUTONEG_RESTART   (1 << 9)
#define MII_BMCR_DUPLEX_MODE       (1 << 8)
#define MII_BMCR_SPEED_MSB         (1 << 6)
#define   MII_BMCR_SPEED_MASK      (1 << 6 | 1 << 13)
#define   MII_BMCR_SPEED_10        (0 << 6 | 0 << 13)
#define   MII_BMCR_SPEED_100       (0 << 6 | 1 << 13)
#define   MII_BMCR_SPEED_1000      (1 << 6 | 0 << 13)
 
/* Basic Mode Status Register (BMSR) bit definitions */
#define MII_BMSR_100BASE_T4        (1 << 15)
#define MII_BMSR_100BASE_X_FULL    (1 << 14)
#define MII_BMSR_100BASE_X_HALF    (1 << 13)
#define MII_BMSR_10_FULL           (1 << 12)
#define MII_BMSR_10_HALF           (1 << 11)
#define MII_BMSR_100BASE_T2_FULL   (1 << 10)
#define MII_BMSR_100BASE_T2_HALF   (1 << 9)
#define MII_BMSR_EXTEND_STATUS     (1 << 8)
#define MII_BMSR_MF_PREAMB_SUPPR   (1 << 6)
#define MII_BMSR_AUTONEG_COMPLETE  (1 << 5)
#define MII_BMSR_REMOTE_FAULT      (1 << 4)
#define MII_BMSR_AUTONEG_ABILITY   (1 << 3)
#define MII_BMSR_LINK_STATUS       (1 << 2)
#define MII_BMSR_JABBER_DETECT     (1 << 1)
#define MII_BMSR_EXTEND_CAPAB      (1 << 0)
 
/* Auto-negotiation Advertisement Register (ANAR) bit definitions */
/* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
#define MII_ADVERTISE_NEXT_PAGE    (1 << 15)
#define MII_ADVERTISE_LPACK        (1 << 14)
#define MII_ADVERTISE_REMOTE_FAULT (1 << 13)
#define MII_ADVERTISE_ASYM_PAUSE   (1 << 11)
#define MII_ADVERTISE_PAUSE        (1 << 10)
#define MII_ADVERTISE_100BASE_T4   (1 << 9)
#define MII_ADVERTISE_100_FULL     (1 << 8)
#define MII_ADVERTISE_100_HALF     (1 << 7)
#define MII_ADVERTISE_10_FULL      (1 << 6)
#define MII_ADVERTISE_10_HALF      (1 << 5)
#define MII_ADVERTISE_SEL_MASK     (0x1F << 0)
#define MII_ADVERTISE_SEL_IEEE_802_3   0x01
 
/* 1000BASE-T Control Register bit definitions */
#define MII_ADVERTISE_1000_FULL    (1 << 9)
#define MII_ADVERTISE_1000_HALF    (1 << 8)
 
#define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
                           MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\
                           MII_ADVERTISE_SEL_IEEE_802_3)
 
/* Extended Status Register bit definitions */
#define MII_ESTAT_1000BASE_X_FULL  (1 << 15)
#define MII_ESTAT_1000BASE_X_HALF  (1 << 14)
#define MII_ESTAT_1000BASE_T_FULL  (1 << 13)
#define MII_ESTAT_1000BASE_T_HALF  (1 << 12)
 
/* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */
#define MII_MMD_ACR_DEVAD_MASK      (0x1F << 0)
#define MII_MMD_ACR_ADDR            (0x00 << 14)
#define MII_MMD_ACR_DATA_NO_POS_INC (0x01 << 14)
#define MII_MMD_ACR_DATA_RW_POS_INC (0x10 << 14)
#define MII_MMD_ACR_DATA_W_POS_INC  (0x11 << 14)
 
#endif /* ZEPHYR_INCLUDE_NET_MII_H_ */