Zephyr API 3.6.99
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arch.h
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1/*
2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
3 * Copyright (c) 2017 Oticon A/S
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
17#ifndef ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_H_
18#define ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_H_
19
20/* Add include for DTS generated information */
21#include <zephyr/devicetree.h>
22
23#include <zephyr/toolchain.h>
24#include <zephyr/irq.h>
28#include <board_irq.h> /* Each board must define this */
29#include <zephyr/sw_isr_table.h>
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36#ifdef CONFIG_64BIT
37#define ARCH_STACK_PTR_ALIGN 8
38#else
39#define ARCH_STACK_PTR_ALIGN 4
40#endif
41
43
44static inline uint32_t arch_k_cycle_get_32(void)
45{
47}
48
50
51static inline uint64_t arch_k_cycle_get_64(void)
52{
54}
55
56static ALWAYS_INLINE void arch_nop(void)
57{
58 __asm__ volatile("nop");
59}
60
61static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
62{
63 return key == false;
64}
65
66static ALWAYS_INLINE unsigned int arch_irq_lock(void)
67{
68 return posix_irq_lock();
69}
70
71
72static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
73{
75}
76
77#ifdef __cplusplus
78}
79#endif
80
81#endif /* ZEPHYR_INCLUDE_ARCH_POSIX_ARCH_H_ */
static ALWAYS_INLINE void arch_nop(void)
Definition arch.h:348
Per-arch thread definition.
#define ALWAYS_INLINE
Definition common.h:129
Devicetree main header.
Public interface for configuring interrupts.
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
Definition arch.h:63
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
Definition arch.h:74
uint64_t sys_clock_cycle_get_64(void)
uint32_t sys_clock_cycle_get_32(void)
static uint32_t arch_k_cycle_get_32(void)
Definition arch.h:99
static uint64_t arch_k_cycle_get_64(void)
Definition arch.h:106
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
Definition arch.h:87
unsigned int posix_irq_lock(void)
void posix_irq_unlock(unsigned int key)
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
Software-managed ISR table.
Macros to abstract toolchain specific capabilities.