9#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MMU_H
10#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_MMU_H
24#define XTENSA_MMU_PERM_X BIT(0)
27#define XTENSA_MMU_PERM_W BIT(1)
30#define XTENSA_MMU_PERM_WX (XTENSA_MMU_PERM_W | XTENSA_MMU_PERM_X)
33#define XTENSA_MMU_CACHED_WB BIT(2)
36#define XTENSA_MMU_CACHED_WT BIT(3)
49#define K_MEM_PARTITION_IS_EXECUTABLE(attr) (((attr) & XTENSA_MMU_PERM_X) != 0)
50#define K_MEM_PARTITION_IS_WRITABLE(attr) (((attr) & XTENSA_MMU_PERM_W) != 0)
51#define K_MEM_PARTITION_IS_USER(attr) (((attr) & XTENSA_MMU_MAP_USER) != 0)
54#define K_MEM_PARTITION_P_RW_U_RW \
55 ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_W | XTENSA_MMU_MAP_USER})
56#define K_MEM_PARTITION_P_RW_U_NA \
57 ((k_mem_partition_attr_t) {0})
58#define K_MEM_PARTITION_P_RO_U_RO \
59 ((k_mem_partition_attr_t) {XTENSA_MMU_MAP_USER})
60#define K_MEM_PARTITION_P_RO_U_NA \
61 ((k_mem_partition_attr_t) {0})
62#define K_MEM_PARTITION_P_NA_U_NA \
63 ((k_mem_partition_attr_t) {0})
66#define K_MEM_PARTITION_P_RX_U_RX \
67 ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_X})
78#define XTENSA_MMU_MAP_USER BIT(4)
90#define XTENSA_MMU_MAP_SHARED BIT(30)
void xtensa_mmu_init(void)
Initialize hardware MMU.
void xtensa_mmu_tlb_shootdown(void)
Invalidate cache to page tables and flush TLBs.
int xtensa_soc_mmu_ranges_num
Number of SoC additional memory regions.
uint32_t k_mem_partition_attr_t
Definition xtensa_mmu.h:47
void xtensa_mmu_reinit(void)
Re-initialize hardware MMU.
void xtensa_mmu_tlb_ipi(void)
Tell other processors to flush TLBs.
const struct xtensa_mmu_range xtensa_soc_mmu_ranges[]
Additional memory regions required by SoC.
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
Struct used to map a memory region.
Definition xtensa_mmu.h:95
const uint32_t end
End address of the memory region.
Definition xtensa_mmu.h:103
const uint32_t attrs
Attributes for the memory region.
Definition xtensa_mmu.h:106
const uint32_t start
Start address of the memory region.
Definition xtensa_mmu.h:100
const char * name
Name of the memory region.
Definition xtensa_mmu.h:97