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◆ GD32_RCU_ADCCK_AHB_DIV3
#define GD32_RCU_ADCCK_AHB_DIV3 3 |
◆ GD32_RCU_ADCCK_AHB_DIV5
#define GD32_RCU_ADCCK_AHB_DIV5 5 |
◆ GD32_RCU_ADCCK_AHB_DIV7
#define GD32_RCU_ADCCK_AHB_DIV7 7 |
◆ GD32_RCU_ADCCK_AHB_DIV9
#define GD32_RCU_ADCCK_AHB_DIV9 9 |
◆ GD32_RCU_ADCCK_APB2_DIV2
#define GD32_RCU_ADCCK_APB2_DIV2 2 |
◆ GD32_RCU_ADCCK_APB2_DIV4
#define GD32_RCU_ADCCK_APB2_DIV4 4 |
◆ GD32_RCU_ADCCK_APB2_DIV6
#define GD32_RCU_ADCCK_APB2_DIV6 6 |
◆ GD32_RCU_ADCCK_APB2_DIV8
#define GD32_RCU_ADCCK_APB2_DIV8 8 |
◆ GD32_RCU_ADCCK_IRC28M
#define GD32_RCU_ADCCK_IRC28M 1 |
◆ GD32_RCU_ADCCK_IRC28M_DIV2
#define GD32_RCU_ADCCK_IRC28M_DIV2 0 |