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#define | PCIE_ID_IS_VALID(id) |
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#define | PCIE_DT_ID(node_id) |
| Get the PCIe Vendor and Device ID for a node.
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#define | PCIE_DT_INST_ID(inst) |
| Get the PCIe Vendor and Device ID for a node.
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#define | DEVICE_PCIE_DECLARE(node_id) |
| Declare a PCIe context variable for a DTS node.
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#define | DEVICE_PCIE_INST_DECLARE(inst) |
| Declare a PCIe context variable for a DTS node.
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#define | DEVICE_PCIE_INIT(node_id, name) |
| Initialize a named struct member to point at a PCIe context.
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#define | DEVICE_PCIE_INST_INIT(inst, name) |
| Initialize a named struct member to point at a PCIe context.
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#define | PCIE_HOST_CONTROLLER(n) |
| Get the BDF for a given PCI host controller.
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#define | PCIE_CONF_CAPPTR 13U /* capabilities pointer */ |
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#define | PCIE_CONF_CAPPTR_FIRST(w) |
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#define | PCIE_CONF_CAP_ID(w) |
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#define | PCIE_CONF_CAP_NEXT(w) |
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#define | PCIE_CONF_EXT_CAPPTR 64U |
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#define | PCIE_CONF_EXT_CAP_ID(w) |
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#define | PCIE_CONF_EXT_CAP_VER(w) |
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#define | PCIE_CONF_EXT_CAP_NEXT(w) |
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#define | PCIE_CONF_ID 0U |
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#define | PCIE_CONF_CMDSTAT 1U /* command/status register */ |
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#define | PCIE_CONF_CMDSTAT_IO 0x00000001U /* I/O access enable */ |
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#define | PCIE_CONF_CMDSTAT_MEM 0x00000002U /* mem access enable */ |
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#define | PCIE_CONF_CMDSTAT_MASTER 0x00000004U /* bus master enable */ |
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#define | PCIE_CONF_CMDSTAT_INTERRUPT 0x00080000U /* interrupt status */ |
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#define | PCIE_CONF_CMDSTAT_CAPS 0x00100000U /* capabilities list */ |
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#define | PCIE_CONF_CLASSREV 2U /* class/revision register */ |
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#define | PCIE_CONF_CLASSREV_CLASS(w) |
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#define | PCIE_CONF_CLASSREV_SUBCLASS(w) |
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#define | PCIE_CONF_CLASSREV_PROGIF(w) |
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#define | PCIE_CONF_CLASSREV_REV(w) |
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#define | PCIE_CONF_TYPE 3U |
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#define | PCIE_CONF_MULTIFUNCTION(w) |
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#define | PCIE_CONF_TYPE_BRIDGE(w) |
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#define | PCIE_CONF_TYPE_GET(w) |
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#define | PCIE_CONF_TYPE_STANDARD 0x0U |
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#define | PCIE_CONF_TYPE_PCI_BRIDGE 0x1U |
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#define | PCIE_CONF_TYPE_CARDBUS_BRIDGE 0x2U |
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#define | PCIE_CONF_BAR0 4U |
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#define | PCIE_CONF_BAR1 5U |
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#define | PCIE_CONF_BAR2 6U |
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#define | PCIE_CONF_BAR3 7U |
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#define | PCIE_CONF_BAR4 8U |
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#define | PCIE_CONF_BAR5 9U |
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#define | PCIE_CONF_BAR_IO(w) |
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#define | PCIE_CONF_BAR_MEM(w) |
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#define | PCIE_CONF_BAR_64(w) |
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#define | PCIE_CONF_BAR_ADDR(w) |
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#define | PCIE_CONF_BAR_IO_ADDR(w) |
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#define | PCIE_CONF_BAR_FLAGS(w) |
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#define | PCIE_CONF_BAR_NONE 0U |
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#define | PCIE_CONF_BAR_INVAL 0xFFFFFFF0U |
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#define | PCIE_CONF_BAR_INVAL64 0xFFFFFFFFFFFFFFF0UL |
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#define | PCIE_CONF_BAR_INVAL_FLAGS(w) |
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#define | PCIE_BUS_NUMBER 6U |
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#define | PCIE_BUS_PRIMARY_NUMBER(w) |
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#define | PCIE_BUS_SECONDARY_NUMBER(w) |
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#define | PCIE_BUS_SUBORDINATE_NUMBER(w) |
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#define | PCIE_SECONDARY_LATENCY_TIMER(w) |
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#define | PCIE_BUS_NUMBER_VAL(prim, sec, sub, lat) |
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#define | PCIE_IO_SEC_STATUS 7U |
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#define | PCIE_IO_BASE(w) |
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#define | PCIE_IO_LIMIT(w) |
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#define | PCIE_SEC_STATUS(w) |
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#define | PCIE_IO_SEC_STATUS_VAL(iob, iol, sec_status) |
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#define | PCIE_MEM_BASE_LIMIT 8U |
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#define | PCIE_MEM_BASE(w) |
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#define | PCIE_MEM_LIMIT(w) |
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#define | PCIE_MEM_BASE_LIMIT_VAL(memb, meml) |
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#define | PCIE_PREFETCH_BASE_LIMIT 9U |
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#define | PCIE_PREFETCH_BASE(w) |
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#define | PCIE_PREFETCH_LIMIT(w) |
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#define | PCIE_PREFETCH_BASE_LIMIT_VAL(pmemb, pmeml) |
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#define | PCIE_PREFETCH_BASE_UPPER 10U |
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#define | PCIE_PREFETCH_LIMIT_UPPER 11U |
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#define | PCIE_IO_BASE_LIMIT_UPPER 12U |
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#define | PCIE_IO_BASE_UPPER(w) |
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#define | PCIE_IO_LIMIT_UPPER(w) |
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#define | PCIE_IO_BASE_LIMIT_UPPER_VAL(iobu, iolu) |
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#define | PCIE_CONF_INTR 15U |
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#define | PCIE_CONF_INTR_IRQ(w) |
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#define | PCIE_CONF_INTR_IRQ_NONE 0xFFU /* no interrupt routed */ |
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#define | PCIE_MAX_BUS (0xFFFFFFFFU & PCIE_BDF_BUS_MASK) |
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#define | PCIE_MAX_DEV (0xFFFFFFFFU & PCIE_BDF_DEV_MASK) |
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#define | PCIE_MAX_FUNC (0xFFFFFFFFU & PCIE_BDF_FUNC_MASK) |
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#define | PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, isr_p, isr_param_p, flags_p) |
| Initialize an interrupt handler for a PCIe endpoint IRQ.
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uint32_t | pcie_conf_read (pcie_bdf_t bdf, unsigned int reg) |
| Read a 32-bit word from an endpoint's configuration space.
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void | pcie_conf_write (pcie_bdf_t bdf, unsigned int reg, uint32_t data) |
| Write a 32-bit word to an endpoint's configuration space.
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int | pcie_scan (const struct pcie_scan_opt *opt) |
| Scan for PCIe devices.
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bool | pcie_get_mbar (pcie_bdf_t bdf, unsigned int bar_index, struct pcie_bar *mbar) |
| Get the MBAR at a specific BAR index.
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bool | pcie_probe_mbar (pcie_bdf_t bdf, unsigned int index, struct pcie_bar *mbar) |
| Probe the nth MMIO address assigned to an endpoint.
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bool | pcie_get_iobar (pcie_bdf_t bdf, unsigned int bar_index, struct pcie_bar *iobar) |
| Get the I/O BAR at a specific BAR index.
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bool | pcie_probe_iobar (pcie_bdf_t bdf, unsigned int index, struct pcie_bar *iobar) |
| Probe the nth I/O BAR address assigned to an endpoint.
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void | pcie_set_cmd (pcie_bdf_t bdf, uint32_t bits, bool on) |
| Set or reset bits in the endpoint command/status register.
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unsigned int | pcie_alloc_irq (pcie_bdf_t bdf) |
| Allocate an IRQ for an endpoint.
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unsigned int | pcie_get_irq (pcie_bdf_t bdf) |
| Return the IRQ assigned by the firmware/board to an endpoint.
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void | pcie_irq_enable (pcie_bdf_t bdf, unsigned int irq) |
| Enable the PCI(e) endpoint to generate the specified IRQ.
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uint32_t | pcie_get_cap (pcie_bdf_t bdf, uint32_t cap_id) |
| Find a PCI(e) capability in an endpoint's configuration space.
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uint32_t | pcie_get_ext_cap (pcie_bdf_t bdf, uint32_t cap_id) |
| Find an Extended PCI(e) capability in an endpoint's configuration space.
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bool | pcie_connect_dynamic_irq (pcie_bdf_t bdf, unsigned int irq, unsigned int priority, void(*routine)(const void *parameter), const void *parameter, uint32_t flags) |
| Dynamically connect a PCIe endpoint IRQ to an ISR handler.
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