Macros
#define	WIFI_MAC_INTR_SOURCE 0

#define	WIFI_MAC_NMI_SOURCE 1

#define	WIFI_PWR_INTR_SOURCE 2

#define	WIFI_BB_INTR_SOURCE 3

#define	BT_MAC_INTR_SOURCE 4

#define	BT_BB_INTR_SOURCE 5

#define	BT_BB_NMI_SOURCE 6

#define	LP_TIMER_SOURCE 7

#define	COEX_SOURCE 8

#define	BLE_TIMER_SOURCE 9

#define	BLE_SEC_SOURCE 10

#define	I2C_MASTER_SOURCE 11

#define	APB_CTRL_INTR_SOURCE 12

#define	GPIO_INTR_SOURCE 13

#define	GPIO_NMI_SOURCE 14

#define	SPI1_INTR_SOURCE 15

#define	SPI2_INTR_SOURCE 16

#define	UART0_INTR_SOURCE 17

#define	UART1_INTR_SOURCE 18

#define	LEDC_INTR_SOURCE 19

#define	EFUSE_INTR_SOURCE 20

#define	RTC_CORE_INTR_SOURCE 21

#define	I2C_EXT0_INTR_SOURCE 22

#define	TG0_T0_LEVEL_INTR_SOURCE 23

#define	TG0_WDT_LEVEL_INTR_SOURCE 24

#define	CACHE_IA_INTR_SOURCE 25

#define	SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26

#define	SYSTIMER_TARGET1_EDGE_INTR_SOURCE 27

#define	SYSTIMER_TARGET2_EDGE_INTR_SOURCE 28

#define	SPI_MEM_REJECT_CACHE_INTR_SOURCE 29

#define	ICACHE_PRELOAD0_INTR_SOURCE 30

#define	ICACHE_SYNC0_INTR_SOURCE 31

#define	APB_ADC_INTR_SOURCE 32

#define	DMA_CH0_INTR_SOURCE 33

#define	SHA_INTR_SOURCE 34

#define	ECC_INTR_SOURCE 35

#define	FROM_CPU_INTR0_SOURCE 36

#define	FROM_CPU_INTR1_SOURCE 37

#define	FROM_CPU_INTR2_SOURCE 38

#define	FROM_CPU_INTR3_SOURCE 39

#define	ASSIST_DEBUG_INTR_SOURCE 40

#define	CORE0_PIF_PMS_SIZE_INTR_SOURCE 41

#define	CACHE_CORE0_ACS_INTR_SOURCE 42

#define	IRQ_DEFAULT_PRIORITY 3

#define	ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */

Macro Definition Documentation

◆ APB_ADC_INTR_SOURCE

#define APB_ADC_INTR_SOURCE 32

◆ APB_CTRL_INTR_SOURCE

#define APB_CTRL_INTR_SOURCE 12

◆ ASSIST_DEBUG_INTR_SOURCE

#define ASSIST_DEBUG_INTR_SOURCE 40

◆ BLE_SEC_SOURCE

#define BLE_SEC_SOURCE 10

◆ BLE_TIMER_SOURCE

#define BLE_TIMER_SOURCE 9

◆ BT_BB_INTR_SOURCE

#define BT_BB_INTR_SOURCE 5

◆ BT_BB_NMI_SOURCE

#define BT_BB_NMI_SOURCE 6

◆ BT_MAC_INTR_SOURCE

#define BT_MAC_INTR_SOURCE 4

◆ CACHE_CORE0_ACS_INTR_SOURCE

#define CACHE_CORE0_ACS_INTR_SOURCE 42

◆ CACHE_IA_INTR_SOURCE

#define CACHE_IA_INTR_SOURCE 25

◆ COEX_SOURCE

#define COEX_SOURCE 8

◆ CORE0_PIF_PMS_SIZE_INTR_SOURCE

#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 41

◆ DMA_CH0_INTR_SOURCE

#define DMA_CH0_INTR_SOURCE 33

◆ ECC_INTR_SOURCE

#define ECC_INTR_SOURCE 35

◆ EFUSE_INTR_SOURCE

#define EFUSE_INTR_SOURCE 20

◆ ESP_INTR_FLAG_SHARED

#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */

◆ FROM_CPU_INTR0_SOURCE

#define FROM_CPU_INTR0_SOURCE 36

◆ FROM_CPU_INTR1_SOURCE

#define FROM_CPU_INTR1_SOURCE 37

◆ FROM_CPU_INTR2_SOURCE

#define FROM_CPU_INTR2_SOURCE 38

◆ FROM_CPU_INTR3_SOURCE

#define FROM_CPU_INTR3_SOURCE 39

◆ GPIO_INTR_SOURCE

#define GPIO_INTR_SOURCE 13

◆ GPIO_NMI_SOURCE

#define GPIO_NMI_SOURCE 14

◆ I2C_EXT0_INTR_SOURCE

#define I2C_EXT0_INTR_SOURCE 22

◆ I2C_MASTER_SOURCE

#define I2C_MASTER_SOURCE 11

◆ ICACHE_PRELOAD0_INTR_SOURCE

#define ICACHE_PRELOAD0_INTR_SOURCE 30

◆ ICACHE_SYNC0_INTR_SOURCE

#define ICACHE_SYNC0_INTR_SOURCE 31

◆ IRQ_DEFAULT_PRIORITY

#define IRQ_DEFAULT_PRIORITY 3

◆ LEDC_INTR_SOURCE

#define LEDC_INTR_SOURCE 19

◆ LP_TIMER_SOURCE

#define LP_TIMER_SOURCE 7

◆ RTC_CORE_INTR_SOURCE

#define RTC_CORE_INTR_SOURCE 21

◆ SHA_INTR_SOURCE

#define SHA_INTR_SOURCE 34

◆ SPI1_INTR_SOURCE

#define SPI1_INTR_SOURCE 15

◆ SPI2_INTR_SOURCE

#define SPI2_INTR_SOURCE 16

◆ SPI_MEM_REJECT_CACHE_INTR_SOURCE

#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 29

◆ SYSTIMER_TARGET0_EDGE_INTR_SOURCE

#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26

◆ SYSTIMER_TARGET1_EDGE_INTR_SOURCE

#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 27

◆ SYSTIMER_TARGET2_EDGE_INTR_SOURCE

#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 28

◆ TG0_T0_LEVEL_INTR_SOURCE

#define TG0_T0_LEVEL_INTR_SOURCE 23

◆ TG0_WDT_LEVEL_INTR_SOURCE

#define TG0_WDT_LEVEL_INTR_SOURCE 24

◆ UART0_INTR_SOURCE

#define UART0_INTR_SOURCE 17

◆ UART1_INTR_SOURCE

#define UART1_INTR_SOURCE 18

◆ WIFI_BB_INTR_SOURCE

#define WIFI_BB_INTR_SOURCE 3

◆ WIFI_MAC_INTR_SOURCE

#define WIFI_MAC_INTR_SOURCE 0

◆ WIFI_MAC_NMI_SOURCE

#define WIFI_MAC_NMI_SOURCE 1

◆ WIFI_PWR_INTR_SOURCE

#define WIFI_PWR_INTR_SOURCE 2

Macros