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#define | GD32_AHBEN_OFFSET 0x14U |
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#define | GD32_APB1EN_OFFSET 0x1CU |
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#define | GD32_APB2EN_OFFSET 0x18U |
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#define | GD32_ADDAPB1EN_OFFSET 0xF8U |
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#define | GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHBEN, 0U) |
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#define | GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) |
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#define | GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) |
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#define | GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) |
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#define | GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U) |
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#define | GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U) |
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#define | GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U) |
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#define | GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U) |
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#define | GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHBEN, 20U) |
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#define | GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHBEN, 22U) |
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#define | GD32_CLOCK_TSI GD32_CLOCK_CONFIG(AHBEN, 24U) |
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#define | GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U) |
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#define | GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) |
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#define | GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) |
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#define | GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U) |
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#define | GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) |
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#define | GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) |
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#define | GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) |
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#define | GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) |
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#define | GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) |
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#define | GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) |
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#define | GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) |
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#define | GD32_CLOCK_CEC GD32_CLOCK_CONFIG(APB1EN, 30U) |
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#define | GD32_CLOCK_CFGCMP GD32_CLOCK_CONFIG(APB2EN, 0U) |
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#define | GD32_CLOCK_ADC GD32_CLOCK_CONFIG(APB2EN, 9U) |
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#define | GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) |
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#define | GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) |
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#define | GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) |
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#define | GD32_CLOCK_TIMER14 GD32_CLOCK_CONFIG(APB2EN, 16U) |
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#define | GD32_CLOCK_TIMER15 GD32_CLOCK_CONFIG(APB2EN, 17U) |
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#define | GD32_CLOCK_TIMER16 GD32_CLOCK_CONFIG(APB2EN, 18U) |
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#define | GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U) |
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