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◆ MAX32_DMA_SLOT_ADC
#define MAX32_DMA_SLOT_ADC 0x09U |
◆ MAX32_DMA_SLOT_I2C0_RX
#define MAX32_DMA_SLOT_I2C0_RX 0x07U |
◆ MAX32_DMA_SLOT_I2C0_TX
#define MAX32_DMA_SLOT_I2C0_TX 0x27U |
◆ MAX32_DMA_SLOT_I2C1_RX
#define MAX32_DMA_SLOT_I2C1_RX 0x08U |
◆ MAX32_DMA_SLOT_I2C1_TX
#define MAX32_DMA_SLOT_I2C1_TX 0x28U |
◆ MAX32_DMA_SLOT_I2C2_RX
#define MAX32_DMA_SLOT_I2C2_RX 0x0AU |
◆ MAX32_DMA_SLOT_I2C2_TX
#define MAX32_DMA_SLOT_I2C2_TX 0x2AU |
◆ MAX32_DMA_SLOT_MEMTOMEM
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U |
◆ MAX32_DMA_SLOT_SPI0_RX
#define MAX32_DMA_SLOT_SPI0_RX 0x0FU |
◆ MAX32_DMA_SLOT_SPI0_TX
#define MAX32_DMA_SLOT_SPI0_TX 0x2FU |
◆ MAX32_DMA_SLOT_SPI1_RX
#define MAX32_DMA_SLOT_SPI1_RX 0x01U |
◆ MAX32_DMA_SLOT_SPI1_TX
#define MAX32_DMA_SLOT_SPI1_TX 0x21U |
◆ MAX32_DMA_SLOT_SPI2_RX
#define MAX32_DMA_SLOT_SPI2_RX 0x02U |
◆ MAX32_DMA_SLOT_SPI2_TX
#define MAX32_DMA_SLOT_SPI2_TX 0x21U |
◆ MAX32_DMA_SLOT_UART0_RX
#define MAX32_DMA_SLOT_UART0_RX 0x04U |
◆ MAX32_DMA_SLOT_UART0_TX
#define MAX32_DMA_SLOT_UART0_TX 0x24U |
◆ MAX32_DMA_SLOT_UART1_RX
#define MAX32_DMA_SLOT_UART1_RX 0x05U |
◆ MAX32_DMA_SLOT_UART1_TX
#define MAX32_DMA_SLOT_UART1_TX 0x25U |
◆ MAX32_DMA_SLOT_UART2_RX
#define MAX32_DMA_SLOT_UART2_RX 0x0EU |
◆ MAX32_DMA_SLOT_UART2_TX
#define MAX32_DMA_SLOT_UART2_TX 0x2EU |