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Zephyr API 3.6.99
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Zephyr API 3.6.99
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Go to the source code of this file.
Enumerations | |
| enum | nios2_creg { NIOS2_CR_STATUS = 0 , NIOS2_CR_ESTATUS = 1 , NIOS2_CR_BSTATUS = 2 , NIOS2_CR_IENABLE = 3 , NIOS2_CR_IPENDING = 4 , NIOS2_CR_CPUID = 5 , NIOS2_CR_EXCEPTION = 7 , NIOS2_CR_PTEADDR = 8 , NIOS2_CR_TLBACC = 9 , NIOS2_CR_TLBMISC = 10 , NIOS2_CR_ECCINJ = 11 , NIOS2_CR_BADADDR = 12 , NIOS2_CR_CONFIG = 13 , NIOS2_CR_MPUBASE = 14 , NIOS2_CR_MPUACC = 15 } |
| #define NIOS2_BSTATUS bstatus |
| #define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) |
| #define NIOS2_CONFIG_REG_ANI_OFST (1) |
| #define NIOS2_CONFIG_REG_ECCEN_MASK (0x00000004) |
| #define NIOS2_CONFIG_REG_ECCEN_OFST (2) |
| #define NIOS2_CONFIG_REG_ECCEXC_MASK (0x00000008) |
| #define NIOS2_CONFIG_REG_ECCEXC_OFST (3) |
| #define NIOS2_CONFIG_REG_PE_MASK (0x00000001) |
| #define NIOS2_CONFIG_REG_PE_OFST (0) |
| #define NIOS2_CPUID cpuid |
| #define NIOS2_ECCINJ_REG_DCDAT_MASK 0x300 |
| #define NIOS2_ECCINJ_REG_DCDAT_OFST 8 |
| #define NIOS2_ECCINJ_REG_DCTAG_MASK 0xc0 |
| #define NIOS2_ECCINJ_REG_DCTAG_OFST 6 |
| #define NIOS2_ECCINJ_REG_DTCM0_MASK 0x3000 |
| #define NIOS2_ECCINJ_REG_DTCM0_OFST 12 |
| #define NIOS2_ECCINJ_REG_DTCM1_MASK 0xc000 |
| #define NIOS2_ECCINJ_REG_DTCM1_OFST 14 |
| #define NIOS2_ECCINJ_REG_DTCM2_MASK 0x30000 |
| #define NIOS2_ECCINJ_REG_DTCM2_OFST 16 |
| #define NIOS2_ECCINJ_REG_DTCM3_MASK 0xc0000 |
| #define NIOS2_ECCINJ_REG_DTCM3_OFST 18 |
| #define NIOS2_ECCINJ_REG_ICDAT_MASK 0x30 |
| #define NIOS2_ECCINJ_REG_ICDAT_OFST 4 |
| #define NIOS2_ECCINJ_REG_ICTAG_MASK 0xc |
| #define NIOS2_ECCINJ_REG_ICTAG_OFST 2 |
| #define NIOS2_ECCINJ_REG_RF_MASK 0x3 |
| #define NIOS2_ECCINJ_REG_RF_OFST 0 |
| #define NIOS2_ECCINJ_REG_TLB_MASK 0xc00 |
| #define NIOS2_ECCINJ_REG_TLB_OFST 10 |
| #define NIOS2_ESTATUS estatus |
| #define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) |
| #define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) |
| #define NIOS2_EXCEPTION_REG_ECCFTL_MASK (0x80000000) |
| #define NIOS2_EXCEPTION_REG_ECCFTL_OFST (31) |
| #define NIOS2_IENABLE ienable |
| #define NIOS2_IPENDING ipending |
| #define NIOS2_MPUACC_C_MASK (0x00000020) |
| #define NIOS2_MPUACC_C_OFST (5) |
| #define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) |
| #define NIOS2_MPUACC_LIMIT_OFST (6) |
| #define NIOS2_MPUACC_MASK_MASK (0xffffffc0) |
| #define NIOS2_MPUACC_MASK_OFST (6) |
| #define NIOS2_MPUACC_PERM_MASK (0x0000001c) |
| #define NIOS2_MPUACC_PERM_OFST (2) |
| #define NIOS2_MPUACC_RD_MASK (0x00000002) |
| #define NIOS2_MPUACC_RD_OFST (1) |
| #define NIOS2_MPUACC_WR_MASK (0x00000001) |
| #define NIOS2_MPUACC_WR_OFST (0) |
| #define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) |
| #define NIOS2_MPUBASE_BASE_ADDR_OFST (6) |
| #define NIOS2_MPUBASE_D_MASK (0x00000001) |
| #define NIOS2_MPUBASE_D_OFST (0) |
| #define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) |
| #define NIOS2_MPUBASE_INDEX_OFST (1) |
| #define NIOS2_NIRQ 32 |
| #define NIOS2_PTEADDR_REG_PTBASE_MASK 0xffc00000 |
| #define NIOS2_PTEADDR_REG_PTBASE_OFST 22 |
| #define NIOS2_PTEADDR_REG_VPN_MASK 0x3ffffc |
| #define NIOS2_PTEADDR_REG_VPN_OFST 2 |
| #define NIOS2_STATUS status |
| #define NIOS2_STATUS_CRS_MSK (0x0000fc00) |
| #define NIOS2_STATUS_CRS_OFST (10) |
| #define NIOS2_STATUS_EH_MSK (0x00000004) |
| #define NIOS2_STATUS_EH_OFST (2) |
| #define NIOS2_STATUS_IH_MSK (0x00000008) |
| #define NIOS2_STATUS_IH_OFST (3) |
| #define NIOS2_STATUS_IL_MSK (0x000003f0) |
| #define NIOS2_STATUS_IL_OFST (4) |
| #define NIOS2_STATUS_NMI_MSK (0x00400000) |
| #define NIOS2_STATUS_NMI_OFST (22) |
| #define NIOS2_STATUS_PIE_MSK (0x00000001) |
| #define NIOS2_STATUS_PIE_OFST (0) |
| #define NIOS2_STATUS_PRS_MSK (0x003f0000) |
| #define NIOS2_STATUS_PRS_OFST (16) |
| #define NIOS2_STATUS_RSIE_MSK (0x00800000) |
| #define NIOS2_STATUS_RSIE_OFST (23) |
| #define NIOS2_STATUS_SRS_MSK (0x80000000) |
| #define NIOS2_STATUS_SRS_OFST (31) |
| #define NIOS2_STATUS_U_MSK (0x00000002) |
| #define NIOS2_STATUS_U_OFST (1) |
| #define NIOS2_TLBACC_REG_C_MASK 0x1000000 |
| #define NIOS2_TLBACC_REG_C_OFST 24 |
| #define NIOS2_TLBACC_REG_G_MASK 0x100000 |
| #define NIOS2_TLBACC_REG_G_OFST 20 |
| #define NIOS2_TLBACC_REG_IG_MASK 0xfe000000 |
| #define NIOS2_TLBACC_REG_IG_OFST 25 |
| #define NIOS2_TLBACC_REG_PFN_MASK 0xfffff |
| #define NIOS2_TLBACC_REG_PFN_OFST 0 |
| #define NIOS2_TLBACC_REG_R_MASK 0x800000 |
| #define NIOS2_TLBACC_REG_R_OFST 23 |
| #define NIOS2_TLBACC_REG_W_MASK 0x400000 |
| #define NIOS2_TLBACC_REG_W_OFST 22 |
| #define NIOS2_TLBACC_REG_X_MASK 0x200000 |
| #define NIOS2_TLBACC_REG_X_OFST 21 |
| #define NIOS2_TLBMISC_REG_BAD_MASK 0x4 |
| #define NIOS2_TLBMISC_REG_BAD_OFST 2 |
| #define NIOS2_TLBMISC_REG_D_MASK 0x1 |
| #define NIOS2_TLBMISC_REG_D_OFST 0 |
| #define NIOS2_TLBMISC_REG_DBL_MASK 0x8 |
| #define NIOS2_TLBMISC_REG_DBL_OFST 3 |
| #define NIOS2_TLBMISC_REG_EE_MASK 0x1000000 |
| #define NIOS2_TLBMISC_REG_EE_OFST 24 |
| #define NIOS2_TLBMISC_REG_PERM_MASK 0x2 |
| #define NIOS2_TLBMISC_REG_PERM_OFST 1 |
| #define NIOS2_TLBMISC_REG_PID_MASK 0x3fff0 |
| #define NIOS2_TLBMISC_REG_PID_OFST 4 |
| #define NIOS2_TLBMISC_REG_RD_MASK 0x80000 |
| #define NIOS2_TLBMISC_REG_RD_OFST 19 |
| #define NIOS2_TLBMISC_REG_WAY_MASK 0xf00000 |
| #define NIOS2_TLBMISC_REG_WAY_OFST 20 |
| #define NIOS2_TLBMISC_REG_WE_MASK 0x40000 |
| #define NIOS2_TLBMISC_REG_WE_OFST 18 |
| #define SYSTEM_BUS_WIDTH 32 |
| enum nios2_creg |
1.12.0