Zephyr API 3.6.99
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Xtensa specific kernel interface header This header contains the Xtensa specific kernel interface. More...
#include <zephyr/irq.h>
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <zephyr/toolchain.h>
#include <zephyr/arch/common/sys_bitops.h>
#include <zephyr/arch/common/sys_io.h>
#include <zephyr/arch/common/ffs.h>
#include <zephyr/sw_isr_table.h>
#include <zephyr/arch/xtensa/syscall.h>
#include <zephyr/arch/xtensa/thread.h>
#include <zephyr/arch/xtensa/irq.h>
#include <xtensa/config/core.h>
#include <zephyr/arch/common/addr_types.h>
#include <zephyr/arch/xtensa/gdbstub.h>
#include <zephyr/debug/sparse.h>
#include <zephyr/arch/xtensa/thread_stack.h>
#include <zephyr/sys/slist.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/arch/xtensa/exception.h>
#include <zephyr/syscalls/arch.h>
Go to the source code of this file.
Data Structures | |
struct | arch_mem_domain |
Macros | |
#define | ARCH_EXCEPT(reason_p) |
#define | ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) |
#define | ARCH_XTENSA_SET_RPO_TLB() |
Setup RPO TLB registers. | |
Functions | |
void | xtensa_arch_except (int reason_p) |
Generate hardware exception. | |
void | xtensa_arch_kernel_oops (int reason_p, void *ssf) |
Generate kernel oops. | |
void | xtensa_user_fault (unsigned int reason) |
static uint32_t | arch_k_cycle_get_32 (void) |
Implementation of arch_k_cycle_get_32. | |
static uint64_t | arch_k_cycle_get_64 (void) |
Implementation of arch_k_cycle_get_64. | |
static ALWAYS_INLINE void | arch_nop (void) |
Implementation of arch_nop. | |
static ALWAYS_INLINE void | xtensa_vecbase_lock (void) |
Lock VECBASE if supported by hardware. | |
static bool | arch_mem_coherent (void *ptr) |
Implementation of arch_mem_coherent. | |
void | arch_xtensa_mmu_post_init (bool is_core0) |
Perform additional steps after MMU initialization. | |
Xtensa specific kernel interface header This header contains the Xtensa specific kernel interface.
It is included by the generic kernel interface header (include/zephyr/arch/cpu.h)
#define ARCH_EXCEPT | ( | reason_p | ) |
#define ARCH_IRQ_CONNECT | ( | irq_p, | |
priority_p, | |||
isr_p, | |||
isr_param_p, | |||
flags_p ) |
#define ARCH_XTENSA_SET_RPO_TLB | ( | ) |
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inlinestatic |
Implementation of arch_k_cycle_get_32.
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inlinestatic |
Implementation of arch_k_cycle_get_64.
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inlinestatic |
Implementation of arch_mem_coherent.
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static |
Implementation of arch_nop.
void arch_xtensa_mmu_post_init | ( | bool | is_core0 | ) |
Perform additional steps after MMU initialization.
This performs additional steps related to memory management after the main MMU initialization code. This needs to defined in the SoC layer. Default is do no nothing.
is_core0 | True if this is called while executing on CPU core #0. |
void xtensa_arch_except | ( | int | reason_p | ) |
Generate hardware exception.
This generates hardware exception which is used by ARCH_EXCEPT().
reason_p | Reason for exception. |
void xtensa_arch_kernel_oops | ( | int | reason_p, |
void * | ssf ) |
Generate kernel oops.
This generates kernel oops which is used by arch_syscall_oops().
reason_p | Reason for exception. |
ssf | Stack pointer. |
void xtensa_user_fault | ( | unsigned int | reason | ) |
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static |
Lock VECBASE if supported by hardware.
The bit 0 of VECBASE acts as a lock bit on hardware supporting this feature. When this bit is set, VECBASE cannot be changed until it is cleared by hardware reset. When the hardware does not support this bit, it is hardwired to 0.